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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40195B MSI 4-bit universal shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 4-bit universal shift register DESCRIPTION The HEF40195B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (O0 to O3), a buffered inverted output from the last bit position (O3) and an overriding asynchronous master reset input (MR). Each register stage is of a D-type master-slave flip-flop. Operation is synchronous (except for MR) and is edge-triggered on the LOW to HIGH transition of the CP HEF40195B MSI input. When PE is LOW, data are loaded into the register from P0 to P3 on the LOW to HIGH transition of CP. When PE is HIGH, data are shifted into the first register position from J and K and all the data in the register are shifted one position to the right on the LOW to HIGH transition of CP. D-type entry is obtained by interconnecting J and K. When J is HIGH and K is LOW, the first stage is in the toggle mode. When J is LOW and K is HIGH, the first stage is in the hold mode. A LOW on MR resets all four bit positions (O0 to O3 = LOW, O3 = HIGH) independent of all other input conditions. Fig.1 Functional diagram. HEF40195BP(N): HEF40195BD(F): HEF40195BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 3 Fig.3 Logic diagram. Philips Semiconductors 4-bit universal shift register HEF40195B MSI Product specification Philips Semiconductors Product specification 4-bit universal shift register PINNING PE P0 to P3 J K CP MR O0 to O3 O3 parallel enable input (active LOW) parallel data inputs first stage J-input (active HIGH) first stage K-input (active LOW) clock input (LOW to HIGH edge triggered) master reset input (active LOW) buffered parallel outputs buffered inverted output from last stage HEF40195B MSI FUNCTION TABLE INPUTS (MR = HIGH) OPERATING MODE PE H shift mode H H H parallel entry mode Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. tn + 1 = state after next LOW to HIGH transition of CP L L J L L H H X X K L H L H X X P0 X X X X L H P1 X X X X L H P2 X X X X L H P3 X X X X L H O0 L O0 O0 H L H OUTPUTS AT tn + 1 O1 O0 O0 O0 O0 L H O2 O1 O1 O1 O1 L H O3 O2 O2 O2 O2 L H O3 O2 O2 O2 O2 H L January 1995 4 Philips Semiconductors Product specification 4-bit universal shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH CP O3 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL 60 30 20 60 30 20 120 60 40 120 60 40 ns ns ns ns ns ns 10 15 tPLH tPHL tPLH tPHL tPLH tPHL 105 50 35 90 45 30 125 50 35 120 50 35 100 45 30 125 55 40 215 95 65 180 85 60 255 100 70 240 105 75 205 90 65 235 115 85 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX. HEF40195B MSI TYPICAL EXTRAPOLATION FORMULA 78 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 63 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 98 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 93 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 98 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL January 1995 5 Philips Semiconductors Product specification 4-bit universal shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Set-up times J, K CP 5 10 15 5 Pn CP 10 15 5 PE CP Hold times J, K CP 10 15 5 10 15 5 Pn CP 10 15 5 PE CP Minimum clock pulse width; LOW Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRMR tWMRL tWCPL thold thold thold tsu tsu tsu SYMBOL MIN. 70 20 10 85 25 10 115 45 30 15 5 0 20 10 0 10 5 5 60 25 20 100 40 30 30 15 15 5 14 19 TYP. 35 10 5 40 10 5 55 20 15 -20 -5 -5 -25 -5 -5 -50 -20 -10 30 10 10 50 20 15 10 5 5 10 28 39 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz HEF40195B MSI see also waveforms Figs 4 and 5 January 1995 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 7 Philips Semiconductors 4-bit universal shift register VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 1900 fi + (foCL) x VDD2 8300 fi + (foCL) x VDD 22 800 fi + (foCL) x VDD 2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) HEF40195B MSI Product specification Fig.4 Waveforms showing set-up times, hold times for J, K and Pn inputs; minimum MR pulse width, MR to output delays and MR to CP recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be specified as negative values. Philips Semiconductors Product specification 4-bit universal shift register HEF40195B MSI Fig.5 Waveforms showing set-up and hold times for PE input. Set-up and hold times are shown as positive values but may be specified as negative values. APPLICATION INFORMATION Some examples of applications for the HEF40195B are: * Serial data transfer * Parallel data transfer * Serial to parallel data transfer * Parallel to serial data transfer January 1995 8 |
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